Please use this identifier to cite or link to this item:
http://hdl.handle.net/10603/460640
Title: | Design of performance enhanced reconfigurable multiplier architecture using vedic multiplication algorithm |
Researcher: | Sivanandam K |
Guide(s): | Kumar P |
Keywords: | Vedic Multiplication Algorithm Multimedia Communication Multiplier Architecture |
University: | Anna University |
Completed Date: | 2021 |
Abstract: | The high configure processors play an important role in the newlineforthcoming technology-led digital era. The processor is the heart of the newlinedigital device because of the processing time, compactness, power newlineconsumption, on-chip and off-chip memory support, inbuilt and external newlineperipherals support, hardware and software support and overall performance newlineof the digital device, all depend on the processor. Furthermore, the newlineprocessorand#8223;s performance depends on the arithmetic and logical unit, data newlinetransfer speed between blocks, and electrical parameters. The arithmetic and newlinelogical unit (ALU) is one of the important blocks to enrich the performance of newlinethe processor. The ALU plays a crucial role in an artificial intelligence-based newlineautomated digital device, big data analysis, robust neural network and newlinemachine learning algorithms, the wireless fourth generation (4G) and fifthgeneration newline(5G) technology, and the Internet of Things (IoT) applications. newlineThe FFT processors need a high-speed arithmetic unit with less critical newlinepath delay. The Fourier analysis can be broadly used in many applications, newlineincluding audio compression, video compression, spectrum analysis, newlinecomparative analysis of DNA sequences, modulation and demodulation of newlinevoice signals in telecommunication systems, various digital signal processors newlinefor wireless communication systems, and so on. Most of the machines newlinelearning algorithms consist of multiplications to compute the input vector. newlineThe fast-growing digital world is looking for high-quality, high-accuracy newlinedigital information with less computation time. High-speed data processing newlinedevices with less power utilization are needed for several audio-visual aid newlineapplications newline |
Pagination: | xxix,163p. |
URI: | http://hdl.handle.net/10603/460640 |
Appears in Departments: | Faculty of Information and Communication Engineering |
Files in This Item:
File | Description | Size | Format | |
---|---|---|---|---|
01_title.pdf | Attached File | 18.28 kB | Adobe PDF | View/Open |
02_prelim pages.pdf | 1.75 MB | Adobe PDF | View/Open | |
03_content.pdf | 92.89 kB | Adobe PDF | View/Open | |
04_abstract.pdf | 92.6 kB | Adobe PDF | View/Open | |
05_chapter 1.pdf | 447.75 kB | Adobe PDF | View/Open | |
06_chapter 2.pdf | 192.52 kB | Adobe PDF | View/Open | |
07_chapter 3.pdf | 4.49 MB | Adobe PDF | View/Open | |
08_chapter 4.pdf | 700.56 kB | Adobe PDF | View/Open | |
09_chapter 5.pdf | 942.97 kB | Adobe PDF | View/Open | |
10_annexures.pdf | 131.63 kB | Adobe PDF | View/Open | |
80_recommendation.pdf | 57.48 kB | Adobe PDF | View/Open |
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