Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/459151
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dc.coverage.spatialDesign approaches for mitigating reliability threats in MPSoC
dc.date.accessioned2023-02-16T11:20:50Z-
dc.date.available2023-02-16T11:20:50Z-
dc.identifier.urihttp://hdl.handle.net/10603/459151-
dc.format.extentxvii,155p.
dc.languageEnglish
dc.relationp.143-154
dc.rightsuniversity
dc.titleDesign approaches for mitigating reliability threats in MPSoC
dc.title.alternative
dc.creator.researcherSatyaraji D
dc.subject.keywordCMOS VLSI Technology
dc.subject.keywordIntegrated Circuits
dc.subject.keywordMPSoC
dc.description.note
dc.contributor.guideBhanumathi V
dc.publisher.placeChennai
dc.publisher.universityAnna University
dc.publisher.institutionFaculty of Information and Communication Engineering
dc.date.registered
dc.date.completed2022
dc.date.awarded2022
dc.format.dimensions21cm
dc.format.accompanyingmaterialNone
dc.source.universityUniversity
dc.type.degreePh.D.
Appears in Departments:Faculty of Information and Communication Engineering

Files in This Item:
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01_title.pdfAttached File242.91 kBAdobe PDFView/Open
02_prelim pages.pdf1.72 MBAdobe PDFView/Open
03_content.pdf617.76 kBAdobe PDFView/Open
04_abstract.pdf186.01 kBAdobe PDFView/Open
05_chapter 1.pdf799.45 kBAdobe PDFView/Open
06_chapter 2.pdf890.21 kBAdobe PDFView/Open
07_chapter 3.pdf1.46 MBAdobe PDFView/Open
08_chapter 4.pdf1.86 MBAdobe PDFView/Open
09_chapter 5.pdf2.55 MBAdobe PDFView/Open
10_chapter 6.pdf802.03 kBAdobe PDFView/Open
11_annexures.pdf2.37 MBAdobe PDFView/Open
80_recommendation.pdf72.65 kBAdobe PDFView/Open


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