Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/459151
Title: Design approaches for mitigating reliability threats in MPSoC
Researcher: Satyaraji D
Guide(s): Bhanumathi V
Keywords: CMOS VLSI Technology
Integrated Circuits
MPSoC
University: Anna University
Completed Date: 2022
Pagination: xvii,155p.
URI: http://hdl.handle.net/10603/459151
Appears in Departments:Faculty of Information and Communication Engineering

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01_title.pdfAttached File242.91 kBAdobe PDFView/Open
02_prelim pages.pdf1.72 MBAdobe PDFView/Open
03_content.pdf617.76 kBAdobe PDFView/Open
04_abstract.pdf186.01 kBAdobe PDFView/Open
05_chapter 1.pdf799.45 kBAdobe PDFView/Open
06_chapter 2.pdf890.21 kBAdobe PDFView/Open
07_chapter 3.pdf1.46 MBAdobe PDFView/Open
08_chapter 4.pdf1.86 MBAdobe PDFView/Open
09_chapter 5.pdf2.55 MBAdobe PDFView/Open
10_chapter 6.pdf802.03 kBAdobe PDFView/Open
11_annexures.pdf2.37 MBAdobe PDFView/Open
80_recommendation.pdf72.65 kBAdobe PDFView/Open
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