Please use this identifier to cite or link to this item:
http://hdl.handle.net/10603/459047
Title: | Design and analysis of reconfigurable sram based fpga architectures |
Researcher: | Swamynathan S M |
Guide(s): | Bhanumathi V |
Keywords: | Field Programmable Gate Array Static Random Access Memory Hardware Trojan |
University: | Anna University |
Completed Date: | 2021 |
Abstract: | The recent developments in wireless communication, Very Large Scale newlineIntegration (VLSI), and embedded system design require a reconfigurable Field newlineProgrammable Gate Array (FPGA) memory system. The reconfigurable FPGA newlinememory system should have the following capabilities such as improved newlinestability, less area, hardware threat free, high speed and energy efficient. FPGA newlineis the most recently used platform for real time applications such as security, newlinenetworking, digital cameras, cell phones, synthesizers, game consoles, aerospace, newlinedefence, medical electronics, ASIC prototyping, automotive, consumer newlineelectronics, distributed monetary systems, high performance computing, industrial, newlinemedical, scientific instruments, security systems and multimedia processing. newlineIn order to improve the stability of reconfigurable systems, it is decided to newlineimplement a stability enhancing Static Random Access Memory (Static newlineRAM or SRAM) cell in FPGA memory systems. SRAM is a type of RAM that newlineuses latching circuitry (flip-flop) to store each bit. The term static differentiates newlineSRAM from dynamic RAM (DRAM), in which DRAM must be newlineperiodically refreshed. SRAM is faster and more expensive than DRAM; it is newlinetypically used for CPU cache while DRAM is used for the main memory of a newlinecomputer. Though it can be characterized as volatile memory, SRAM newlineexhibits data remanence. SRAM offers a simple data access model and does not newlinerequire a refresher circuit. SRAM is classified as Non-volatile SRAM and newlinePseudo SRAM. By transistor type it is divided into (i) Bipolar junction newlinetransistor (used in TTL and ECL) It can provide very fast operation but with newlinehigh power consumption. (ii) MOSFET (used in CMOS) - It is of low power newlineconsuming and very common today. Based on flip-flop type, it is divided into newline(i) Binary SRAM and (ii) Ternary SRAM. newline |
Pagination: | xv,132p. |
URI: | http://hdl.handle.net/10603/459047 |
Appears in Departments: | Faculty of Information and Communication Engineering |
Files in This Item:
File | Description | Size | Format | |
---|---|---|---|---|
01_title.pdf | Attached File | 43.58 kB | Adobe PDF | View/Open |
02_prelim pages.pdf | 1.77 MB | Adobe PDF | View/Open | |
03_content.pdf | 284.84 kB | Adobe PDF | View/Open | |
04_abstract.pdf | 101.92 kB | Adobe PDF | View/Open | |
05_chapter 1.pdf | 278.94 kB | Adobe PDF | View/Open | |
06_chapter 2.pdf | 758.56 kB | Adobe PDF | View/Open | |
07_chapter 3.pdf | 813.75 kB | Adobe PDF | View/Open | |
08_chapter 4.pdf | 622.51 kB | Adobe PDF | View/Open | |
09_chapter 5.pdf | 131.84 kB | Adobe PDF | View/Open | |
10_annexures.pdf | 106.99 kB | Adobe PDF | View/Open | |
80_recommendation.pdf | 84.56 kB | Adobe PDF | View/Open |
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