Design and analysis of low power high speed domino logic circuits with improved noise immunity

Abstract

The demands for high performance computing of VLSI hardware design enforce the digital designers towards the CMOS Dynamic logic style. Dynamic logic is mainly used for its high speed with less silicon area. However, the main drawback of CMOS logic style is its low noise tolerance (Frustaciet al. 2007) (Wey et al. 2008). Generally, the noise tolerance is improved at the cost of speed degradation and high-power consumption. This problem is severe with the continuous scaling of hardware (Hernandez 2006). Therefore, designing the high-speed low power circuits without affecting the noise tolerance is very much needed in high performance signal processing(Larsson and Svensson 1994)( 0. Gonzalez-Diaz et al. 2006). The intention of the research work is designing high speed, low power VLSI circuits design without compromising noise immunity. newlineIn this research work, Node Voltage based Conditional Keeper is proposed for achieving high speed and low power in domino logic circuit with good noise immunity. The Proposed Node Voltage based Conditional Keeper has attained better power delay product with good noise tolerance as compared to previous domino logic designs. newline newline