Design and implementation of 16 bit counter with various logic using process variation technology

Abstract

The utilization of usual supply voltage and clock for repetitive state newlinetransistors in digital circuits is a fundamental driver for high power utilization. newlineThe proposed two approaches are Control Logic (CL) with Integrated newlineClock Gating (ICG) and Programmable Combinational Logic (PCL) and newlineGate Logic (GL) with ICG to achieve the low power and low dynamic newlineleakage in 16-bit Counter. These approaches operate in different Logic to newlineGenerate/stop the clock for low-power digital circuits. The First approach newlineof control Logic with ICG stops the clock only for single Most Significant newlineFlip Flop Transistor. This approach consumes 1.6 mW and 15% more newlinepower savings than Existing. But the second approach only consumes newline0.0261 mW power, which is 98% more power savings than a first newlineproposed approach of CL with ICG and conventional counters. These newlinedramatic boom power savings by stopping the clock for all redundant newlinetransition in Most Significant Flip Flop Transistors using PCL and GL with newlineICG. Analyse the second approach without ICG for 16-bit counter will newlineconsume 0.0334 mW, which consumes 21.96% high power than the newlinepresence of ICG in counter circuits. Moreover, the same proposed newlinetechnique of the second approach applies for ISCAS 89 S444 circuits, newlinewhich saves gt90% power improvement than the conventional method and newlineordinary 16-bit counter-power analysis by the same technology, which newlineconsumes 42.42% high power than pro- posed low-power counter. The newlineLow Power 16-bit counter design implementation using 16 nm Cadence newlineGenus technology, which attains the dynamic leakage with ICG is newline0.170nW and without ICG is 0.177nW with an operating voltage of 0.8 V. newline