Certain investigations on the design and analysis of power efficient radix multiplier using quaternary signed digit number system for signal processing applications

Abstract

With the exponential increase of data processing and storage needs, there is a strong momentum to move to a higher radix logic/number system that can exterminate many limitations of the binary system is presented in Lazzari C et al. (2009). Awaited saturation of Moore s law and the necessity to increase information density and processing speed in the future micro and nanoelectronic circuits and systems provide a strong background and motivation for the beyond-binary logic system. newlineFor low power and real-time applications, computationally intensive digital signal processing algorithms are implemented in Dedicated VLSI systems. The Multiplier is one of the most crucial parts of such systems. The computation speed of a processor is highly dependent on these arithmetic units. In the conventional multiplier, the number of partial products is determined by the number of bits the multiplicand or multiplier is used. If the number of bits in the multiplicand increases, it took a long time to produce the product. The radix-4 algorithm is widely used to improve the performance of the multiplier because it can reduce the number of partial products by half. newlineThe researchers in VLSI Technology have been engaged in Multi-valued logic circuits (Quaternary) for the past few years, the intention behind the statement that some synonymous with multiple-valued logic is the of theory and application of logic, where the traditional truth values true and false are switched by several values. newline