1. Shodhganga@INFLIBNET
  2. Indian Institute of Technology Hyderabad
  3. Department of Electrical Engineering
Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/455374
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DC FieldValueLanguage
dc.coverage.spatialElectrical Engineering
dc.date.accessioned2023-01-31T06:02:57Z-
dc.date.available2023-01-31T06:02:57Z-
dc.identifier.urihttp://hdl.handle.net/10603/455374-
dc.description.abstractAvailable newline newline
dc.format.extentxi, 155 p.
dc.languageEnglish
dc.relationNA
dc.rightsuniversity
dc.titleVariability aware cmos device design and simulations of sub 10 nm confined geometry nano mosfets
dc.title.alternativeNa
dc.creator.researcherS., Akhil
dc.subject.keywordEngineering
dc.subject.keywordEngineering and Technology
dc.subject.keywordEngineering Electrical and Electronic
dc.description.noteReference page p. 136
dc.contributor.guideNayak, Kaushik
dc.publisher.placeKandi
dc.publisher.universityIndian Institute of Technology Hyderabad
dc.publisher.institutionDepartment of Electrical Engineering
dc.date.registered2015
dc.date.completed2021
dc.date.awarded2022
dc.format.dimensionsNA
dc.format.accompanyingmaterialDVD
dc.source.universityUniversity
dc.type.degreePh.D.
Appears in Departments:Department of Electrical Engineering

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80_recommendation.pdf532.45 kBAdobe PDFView/Open
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