Design and implementation of modified cordic based reconfigurable fft architecture for iot applications

Abstract

A Fast Fourier Transform (FFT) is an efficient algorithm for calculating a Discrete Fourier Transformation (DFT). It is one of the most notable operations in modern DSP systems and it is used to deliver a fast approach for the processing of data in wireless transmissions. Fast Fourier Transformation (FFT) is the most prevalent algorithm for spectral analysis of acoustic emission signals acquired at ultra-high sampling rates. In this research, efficient hardware architecture is established for the implementation of CORDIC FFT based on the radix-2 decimation in frequency algorithm (R2DIF) and a pipelined technique that allows data to be effectively shared through storage via shift registers. For instance, it can perform FFT size of 64,128 and 512 points that can be communicated as powers of various radices. The design incorporates an optimal rotation scheme using the modified coordinate rotation digital computer (m-CORDIC) algorithm by adopting an odd angle storage algorithm and a Radix- 2r based coding scheme to replace the complex multipliers in FFT to achieve high speed and low power architecture. The m-CORDIC algorithm improves the convergence of computation, while the Radix-2r allows a logarithmic reduction of the adder steps. The established pipelined FFT processor uses only the distributed logical resources and it does not require expensive dedicated functional blocks. An effective implementation of FFT in FPGA can be transferred without much effort to a fully customized ASIC to reduce the cost of large-scale device production. newline