Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/454255
Title: Design and implementation of high Performance digital circuits using Quantum dot cellular automata in Nanotechnology
Researcher: Jeyalakshmi, M
Guide(s): Santhi, M
Keywords: Engineering and Technology
Engineering
Engineering Electrical and Electronic
digital circuits
Quantum dot cellular automata
Nanotechnology
University: Anna University
Completed Date: 2021
Abstract: With a view to keep CMOS technology appropriate to Moore s law, a number of solutions have been proposed. In spite of those proposals, these solutions also face quite a few restrictions and constrictions. This has boosted the research to discover alternative technologies, to design circuits at extreme nanometer levels. Quantum-dot Cellular Automata (QCA) has become one of the best technologies. newlineRecently, the QCA realizations of the Adders, Subtractors and Code converters, which are the most frequently used digital circuits, have become the topic of considerably numerous research papers. In this research, a novel coplanar QCA 1-bit Full Adder circuit is proposed which is designed with a minimum number of QCA cells. The proposed Full Adder requires only 13 QCA cells, an area of 0.008 and#956;m2 and a delay of about 2 clock cycles to implement its function. Then an efficient 4-bit Ripple Carry Adder (RCA) is designed based on the proposed Full Adder to perform higher-end addition which requires only 70 QCA cells, an area of 0.18 and#956;m2 and delay of about 5 clock cycles to implement its function in an effective way. Simulation results are obtained precisely using the QCA designer tool version 2.0.3. From the comparisons, it is found that our work achieves over 55% of improvement in QCA cell count. newlineA Subtractor is an important arithmetic circuit used in many digital circuits. An efficient 1-bit Full Subtractor using multilayer crossover is proposed using majority logic in QCA. The proposed design has only 53 cells and occupies a small area of about 0.03 and#956;m2. Using the proposed Subtractor, a 4-bit Ripple Borrow Subtractor (RBS) with 256 cells and an area of about 0.20 and#956;m2 is realized. Verification and simulations are done using QCA Designer. newline
Pagination: xviii,138p.
URI: http://hdl.handle.net/10603/454255
Appears in Departments:Faculty of Information and Communication Engineering

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02_prelim pages.pdf1.38 MBAdobe PDFView/Open
03_content.pdf220.66 kBAdobe PDFView/Open
04_abstract.pdf129.33 kBAdobe PDFView/Open
05_chapter 1.pdf1.26 MBAdobe PDFView/Open
06_chapter 2.pdf583.33 kBAdobe PDFView/Open
07_chapter 3.pdf623.41 kBAdobe PDFView/Open
08_chapter 4.pdf604.38 kBAdobe PDFView/Open
09_chapter 5.pdf1.17 MBAdobe PDFView/Open
10_chapter 6.pdf1.78 MBAdobe PDFView/Open
11_annexures.pdf108.58 kBAdobe PDFView/Open
80_recommendation.pdf89.24 kBAdobe PDFView/Open
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