Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/454125
Title: Design and development of Non modular multilevel inverter Topologies for device count waning
Researcher: Kannan, C
Guide(s): Nalinkant Mohanty
Keywords: Engineering and Technology
Computer Science
Telecommunications
Multilevel inverter
Reduced switch
Flexible Rung Ladder
University: Anna University
Completed Date: 2021
Abstract: Recent developments in the field of power electronics supported by newlinethe structural inovations in power conversion circuits and their operational newlineflexibility motivate to develop various multilevel inverter (MLI) topologies newlinecompatible for various applications like renewable energy systems, electric newlinedrives and other low/medium power applications. Inherently the MLI can newlinesynthesize a high quality ac output voltage of required frequency from multiple newlineseparate/isolated dc sources (SDCs) with merits such as lower dv/dt and device newlinestresses, a diminsihed output voltage distortion, minimal switching losses, and newlinehaving ability to operate at higher voltages. newlineThe main objective of this thesis is to propose three different novel newlineMLI structures to mitigate the issues like the objectionable component count, newlinehigher number of active devices in the conduction path and more conduction newlinelosses. First, a flexible rung ladder structured MLI (FRLSMLI) structure is newlineproposed with the dual mode capability (both symmetrical and asymmetrical newlinemodes), which paves the solution to the above mentioned problems. A tapped newlinesource stack succored modified HX bridge MLI (TSSSMHXBMLI) to trim the newlinetotal count of power components is proposed secondly. Finally, a matrix newlinestructure, involving switches in columns and SDCs in the row links, to wane newlinethe total component count is developed, by introducing the cross switching in newlinethe structure to curtail the number of switching devices in the current newlineconduction path in all output voltage levels. newline
Pagination: xvii,114p.
URI: http://hdl.handle.net/10603/454125
Appears in Departments:Faculty of Information and Communication Engineering

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01_title.pdfAttached File352.67 kBAdobe PDFView/Open
02_prelim pages.pdf1.22 MBAdobe PDFView/Open
03_content.pdf84.95 kBAdobe PDFView/Open
04_abstract.pdf37.4 kBAdobe PDFView/Open
05_chapter 1.pdf145.4 kBAdobe PDFView/Open
06_chapter 2.pdf273.34 kBAdobe PDFView/Open
07_chapter 3.pdf1.7 MBAdobe PDFView/Open
08_chapter 4.pdf949.82 kBAdobe PDFView/Open
09_chapter 5.pdf1.06 MBAdobe PDFView/Open
10_annexures.pdf141.26 kBAdobe PDFView/Open
80_recommendation.pdf126.23 kBAdobe PDFView/Open
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