1. Shodhganga@INFLIBNET
  2. International Institute of Information Technology, Hyderabad
  3. Department of Electronic and Communication Engineering
Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/45300
Title: Design of efficient VLSI arithmetic circuits
Researcher: Veeramachaneni, Sreehari
Guide(s): Srinivas, M B
Keywords: Adders
Compressor
Counter
Decrement
Floating point
Increment
Multipliers
Upload Date: 21-Jul-2015
University: International Institute of Information Technology, Hyderabad
Completed Date: 23/06/2015
Abstract: Abstract Available
Pagination: xv, 123p.
URI: http://hdl.handle.net/10603/45300
Appears in Departments:Department of Electronic and Communication Engineering

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01_title.pdfAttached File295.12 kBAdobe PDFView/Open
02_certificate.pdf138.82 kBAdobe PDFView/Open
03_acknowlegment.pdf295.03 kBAdobe PDFView/Open
04_abstract.pdf294.99 kBAdobe PDFView/Open
05_content .pdf294.76 kBAdobe PDFView/Open
06_list of figures.pdf295.47 kBAdobe PDFView/Open
07_list of tables.pdf294.32 kBAdobe PDFView/Open
08_chapter 1.pdf1.68 MBAdobe PDFView/Open
09_chapter 2.pdf1.68 MBAdobe PDFView/Open
10_chapter 3.pdf1.68 MBAdobe PDFView/Open
11_chapter 4.pdf1.68 MBAdobe PDFView/Open
12_chapter 5.pdf1.68 MBAdobe PDFView/Open
13_chapter 6.pdf1.68 MBAdobe PDFView/Open
14_chapter 7.pdf1.68 MBAdobe PDFView/Open
15_chapter 8.pdf1.68 MBAdobe PDFView/Open
16_reference.pdf162.84 kBAdobe PDFView/Open
17_publication.pdf136.96 kBAdobe PDFView/Open
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