Performance analysis Of lte physical layer and its implementation Using reconfigurable architecture

Abstract

Despite their increasing success over the years, wireless newlinetechnology face challenges, like multipath, interference and spectrum newlinelimitations. Among them, a new air interface for mobile newlinecommunications was introduced called the Long Term Evolution. The newlinestandardization work of the 3rd Generation Partnership Project along newlinewith the Universal mobile telephone system has given rise to the LTE. newlineThis research focuses primarily on the research developments which newlinetarget the physical layer. As a part of the LTE survey, simulation tools newlineare presented to demonstrate the need for hardware co-simulation. newlineFollowing the feasibility study, the value of the model is to be evaluated newlineclosely with the supporting inferences and the comparison of various newlinewireless network simulators appropriate for LTE. The roadmap for the newlinework in Hardware Co simulation with system generator and the newlineMATLAB / SIMULINK is also defined from this analysis. The System newlineGenerator integrated with MATLAB provides hardware extension and newlinemapping with FPGA modules. newlineThe first step is to examine the physical layer of the Long Term newlineEvolution in Simulink environment with different modulation newlinetechniques, channel modulation, and antenna configuration, by newlineexamining the bit error rate. For this analysis, the OFDMA, SC-FDMA newlineTransmission System was analyzed. The second stage is the use of newlineFPGAs and how it can be configured as Hardware in Loop for validation newlinealong with Simulink and Xilinx System Generator. Furthermore, their newlinecompatibility is indicated for long-term use and communication newlinedurability. In the third stage results may be discussed in terms of newlinex newlineRegister transfer level design, power estimation, and resource newlineestimation. For synthesis Spartan6, Virtex 7, Spartan 7, Artix 7, and newlineKintex 7 board is used and for implementation of the above architecture newlineSpartan6 board is used.In conclusion the Timing summary as the newlinemaximum path delay is 3.150 ns for Spartan 6 Board, the remaining newlinedevices producing the path delay is 0.405 ns. The maximum power newlineprovided by the Virtex board in c