On chip emi mitigation approaches using novel clock generator based low power vlsi architectures

Abstract

newline In the modern world, each and every device is prone to electromagnetic interference (EMI) either by the device itself or from its neighborhood. In particular, clock signal plays a vital role in producing EMI in digital devices as it swings between high and low alternating states. Unattended EMI leads to damage of the device itself or other nearby devices. The increase of clock frequency in VLSI circuits strengthens the EMI between devices. Nowadays, EMC/EMI is rapidly becoming a major concern for high-speed digital circuits. The main aim of this research is the reduction of EMI by employing novel clock generators suitable for specific applications .In this research, spread spectrum clocking, modified edge combiner, open loop clock generator, and chaotic modulator based approaches have been proposed to mitigate the EMI. In the first approach, the proposed all-digital spread spectrum clock generator with sawtooth modulator is used for modulating the system clock to combat the effects of EMI efficiently. Compared with triangular modulation, saw tooth modulation approach utilizes only up counters thereby reducing the complexity. Sharp peak in the clock spectrum is spread to reduce the EMI. Narrow band spectral peak is dispersed to extensive band. Also the RMS jitter is found to be 3.88ps and the EMI reduction with spread and without spread were found to be 28.28 dB and 14.14 dB respectively. An EMI reduction of 14.14 dB is achieved by spreading the clock.