Study and performance analysis of various truncated multiplier for low power vlsi

Abstract

newline Recently, the digital circuitry needs the decrease of area and power newlineby optimizing the time with improving performance in speed. The newlinefundamental digital circuits consist of adders and multipliers as their newlinebuilding blocks. So, the performance of adders and multipliers must be newlineimproved to enhance the performance of real-world integrated circuits. newlineInitially, this research is focused on implementation of novel newlinearchitecture of modified carry select adder utilizing full carry generation, newlinefull sum generation, half carry generation, and half sum generation blocks, newlinewhich is named as half sum carry generation- sum carry selection - carry newlineselect adder (HSCG-SCS-CSLA). Further, the sum and carry output newlinegeneration consumes less propagation time by utilizing multiplexer newlineswitching logic, which selects the full sum bits and carry bits in high-speed newlinemanner. The simulation results show that the proposed HSCG-SCS-CSLA newlineresulted in improved area, delay and power consumptions as compared to newlinethe basics adders and state-of-art approaches. newlineSecondly, this research is focused on implementation of truncation newlinemultiplier using HSCG-SCS-CSLA, which enhances its performance by newlinereducing the number of partial product generations, additions, and newlinecomputations. Further, the performance of proposed HSCG-SCS-CSLA newlinebased truncated multiplier is compared with conventional methods such as newlinetruncated multiplier utilizing square root-CSLA, Common Boolean Logic newlinebased CSLA and Ripple carry adder with binary to excess converter based