LongLiveNoC Wear Levelling Write Reduction and Selective VC allocation for Long lasting Dark Silicon aware NoC Interconnects

Abstract

Increasing processing demand has led to the newlinedevelopment of chip multiprocessors which can have multiple to many cores newlineconnected with each other and with the on-chip caches. These connections are newlineestablished by an on-chip packet switched Network-on-Chip (NoC). Scaling of newlinetechnology nodes increases the power dissipated by the chips leading to thermal newlinerestrictions. To control the chip thermal design power, certain components (like newlinecores and caches) may be turned off. However, in this scenario of dark silicon, the newlineinterconnect is expected to be available.