Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/450417
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dc.date.accessioned2023-01-20T04:45:07Z-
dc.date.available2023-01-20T04:45:07Z-
dc.identifier.urihttp://hdl.handle.net/10603/450417-
dc.description.abstractIncreasing processing demand has led to the newlinedevelopment of chip multiprocessors which can have multiple to many cores newlineconnected with each other and with the on-chip caches. These connections are newlineestablished by an on-chip packet switched Network-on-Chip (NoC). Scaling of newlinetechnology nodes increases the power dissipated by the chips leading to thermal newlinerestrictions. To control the chip thermal design power, certain components (like newlinecores and caches) may be turned off. However, in this scenario of dark silicon, the newlineinterconnect is expected to be available.
dc.format.extent
dc.languageEnglish
dc.relation
dc.rightsself
dc.titleLongLiveNoC Wear Levelling Write Reduction and Selective VC allocation for Long lasting Dark Silicon aware NoC Interconnects
dc.title.alternativeN.A.
dc.creator.researcherRani, Khushboo
dc.subject.keywordComputer Science
dc.subject.keywordComputer Science Interdisciplinary Applications
dc.subject.keywordEngineering and Technology
dc.description.note
dc.contributor.guideKapoor, Hemangee Kalpesh
dc.publisher.placeGuwahati
dc.publisher.universityIndian Institute of Technology Guwahati
dc.publisher.institutionDepartment of Computer Science and Engineering
dc.date.registered2012
dc.date.completed2021
dc.date.awarded2021
dc.format.dimensions
dc.format.accompanyingmaterialNone
dc.source.universityUniversity
dc.type.degreePh.D.
Appears in Departments:Department of Computer Science and Engineering

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