1. Shodhganga@INFLIBNET
  2. Indian Institute of Technology Patna
  3. Department of Electrical Engineering
Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/450393
Title: Design and Optimization of CMOS Devices for Dynamic Memories and Spiking Neural Networks
Researcher: Neha Kamal
Guide(s): Jawar Singh
Keywords: Engineering
Engineering and Technology
Engineering Electrical and Electronic
University: Indian Institute of Technology Patna
Completed Date: 2022
Abstract: newline
Pagination: xxiv, 126
URI: http://hdl.handle.net/10603/450393
Appears in Departments:Department of Electrical Engineering

Files in This Item:
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01_title.pdfAttached File274.99 kBAdobe PDFView/Open
02_prelim pages.pdf11.62 MBAdobe PDFView/Open
03_content.pdf1.57 MBAdobe PDFView/Open
04_abstract.pdf1.93 MBAdobe PDFView/Open
05_chapter 1.pdf6.37 MBAdobe PDFView/Open
06_chapter 2.pdf18.55 MBAdobe PDFView/Open
07_chapter 3.pdf10.81 MBAdobe PDFView/Open
08_chapter 4.pdf8.62 MBAdobe PDFView/Open
09_chapter 5.pdf7.8 MBAdobe PDFView/Open
10_chapter 6.pdf10.86 MBAdobe PDFView/Open
11_chapter 7.pdf1.96 MBAdobe PDFView/Open
12_annexures.pdf17.54 MBAdobe PDFView/Open
80_recommendation.pdf539.59 kBAdobe PDFView/Open
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