Implementation of Modified hybrid model encryption algorithm Using vlsi

Abstract

newlineIn this new era of digital pedagogy, everything is being newlinecommunicated on time through the internet or other communication newlinemedia. A few trends in digital pedagogy are smart phones, block chain, newlineautomation devices, eBay, face recognition systems, health monitoring newlinedevices, etc. These applications are more reliant on data transmission, newlinemedia, protocols and, more importantly security. In some cases, security newlinechallenges are raised to the next level such as data theft, public and newlineprivate key hacking, bit-stream hacking, authentication and newlineconfidentiality, etc. To meet all these challenges, researchers have newlinedeveloped efficient cryptographic algorithms for secured data newlineencryption and decryption process. Developing a secured environment newlinefor these applications has been a hot topic in recent research. Several newlinereal-time problems, such as massive power consumption and significant newlinecomputing complexity, arise when designing such safe systems. Unique newlinecypher transformation technique with minimal complexity is needed in newlineparticular for small energy and resource restricted wireless sensor newlinenetwork applications. To overcome all these challenges, an intellectual newlinecryptosystem is proposed with hierarchical hardware pipelined newlinestructures. An additional goal of the proposed framework is to enhance newlinethe area efficiency, throughput and optimize the hardware structures. newlineIn this work, two different cryptosystems are introduced in newlineterms of hybrid methods and novel architecture. Initially, block cipher is newlinecombined with stream cipher as encryption systems. Advanced newlinevi newlineEncryption Standards (AES) and Rivest Cipher 4(RC4) are considered newlineblock and stream ciphers. This hybrid technique improved the area, newlinethroughput and power consumption. Finally parallel sub pipelined newlinetechniques and on-the-fly encryption algorithms are combined newlineconcurrently. The proposed algorithms are experimentally tested in the newlineField Programmable Gate Array (FPGA) platform and the performance newlinein terms of area efficiency, throughput and power traces is evaluated