Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/449877
Full metadata record
DC FieldValueLanguage
dc.coverage.spatialNA
dc.date.accessioned2023-01-19T09:46:49Z-
dc.date.available2023-01-19T09:46:49Z-
dc.identifier.urihttp://hdl.handle.net/10603/449877-
dc.description.abstractnewline
dc.format.extentNA
dc.languageEnglish
dc.relationNA
dc.rightsuniversity
dc.titleMGDI Based Reliable Low Power Memory Design with Clock Splitting MBIST
dc.title.alternativeNA
dc.creator.researcherDannina, S Sambasiva Rao
dc.subject.keywordEngineering
dc.subject.keywordEngineering and Technology
dc.subject.keywordEngineering Electrical and Electronic
dc.description.noteNA
dc.contributor.guideKumar, Sunil
dc.publisher.placeRaipur
dc.publisher.universityKalinga University
dc.publisher.institutionFaculty of Engineering
dc.date.registered2017
dc.date.completed2022
dc.date.awarded2022
dc.format.dimensionsNA
dc.format.accompanyingmaterialNone
dc.source.universityUniversity
dc.type.degreePh.D.
Appears in Departments:Faculty of Engineering

Files in This Item:
File Description SizeFormat 
01_title.pdfAttached File7.35 MBAdobe PDFView/Open
02_prelim pages.pdf1.64 MBAdobe PDFView/Open
03_content.pdf6.91 MBAdobe PDFView/Open
04_abstract.pdf7.68 MBAdobe PDFView/Open
05_chapter 1.pdf7.35 MBAdobe PDFView/Open
06_chapter 2.pdf7.35 MBAdobe PDFView/Open
07_chapter 3.pdf7.35 MBAdobe PDFView/Open
08_chapter 4.pdf7.35 MBAdobe PDFView/Open
09_chapter 5.pdf7.35 MBAdobe PDFView/Open
10_annexures.pdf7.65 MBAdobe PDFView/Open
11_chapter 6.pdf7.35 MBAdobe PDFView/Open
12_chapter 7.pdf7.35 MBAdobe PDFView/Open
13_chapter 8.pdf7.35 MBAdobe PDFView/Open
14_chapter 9.pdf7.35 MBAdobe PDFView/Open
15_chapter 10.pdf7.35 MBAdobe PDFView/Open
80_recommendation.pdf8.63 MBAdobe PDFView/Open


Items in Shodhganga are licensed under Creative Commons Licence Attribution-NonCommercial-ShareAlike 4.0 International (CC BY-NC-SA 4.0).

Altmetric Badge: