1. Shodhganga@INFLIBNET
  2. Jawaharlal Nehru Technological University, Kakinada
  3. Department of Electronics and Communication Engineering
Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/448562
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DC FieldValueLanguage
dc.coverage.spatial
dc.date.accessioned2023-01-18T05:56:32Z-
dc.date.available2023-01-18T05:56:32Z-
dc.identifier.urihttp://hdl.handle.net/10603/448562-
dc.description.abstractnewline
dc.format.extent
dc.languageEnglish
dc.relation
dc.rightsuniversity
dc.titlePerformance Evaluation of Improved Low Power March based Memory Test Algorithms for Testing SRAM
dc.title.alternative
dc.creator.researcherG. Rajesh Kumar
dc.subject.keywordEngineering
dc.subject.keywordEngineering and Technology
dc.subject.keywordEngineering Electrical and Electronic
dc.description.note
dc.contributor.guideK.Babulu
dc.publisher.placeKakinada
dc.publisher.universityJawaharlal Nehru Technological University, Kakinada
dc.publisher.institutionDepartment of Electronics and Communication Engineering
dc.date.registered2012
dc.date.completed2021
dc.date.awarded2021
dc.format.dimensions
dc.format.accompanyingmaterialDVD
dc.source.universityUniversity
dc.type.degreePh.D.
Appears in Departments:Department of Electronics and Communication Engineering

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