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http://hdl.handle.net/10603/448293
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DC Field | Value | Language |
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dc.coverage.spatial | ||
dc.date.accessioned | 2023-01-18T04:19:09Z | - |
dc.date.available | 2023-01-18T04:19:09Z | - |
dc.identifier.uri | http://hdl.handle.net/10603/448293 | - |
dc.description.abstract | Digital filter is the basic building block of any digital signal processing application. Among the different digital filters available, Finite impulse response (FIR) filter is used in most of the applications because of its prominent advantages like stability and linear phase response. The FIR filter does mathematical computation like multiplication and addition on the input discrete signal to provide the desired discrete output signal. The real time applications such as satellite signal processing, radar signal processing and speech signal processing requires dedicated hardware and efficient FIR filter which can work with high speed. Portable and small sized application like hearing aids and mobiles need to operate on limited power supplies. Thus there is requirement of area-power and speed efficient de sign of FIR filters. Among the computing operators used in FIR filter, multipliers are complex and cost effective. An efficient design of multiplier improves the efficiency of the FIR filter. The implementation of the FIR filter can be varied as per the nature of the coefficients of the filter. One is fixed coefficient implementation and the other is adaptive coefficient implementation. The hardware implementation of these two types of filter is different. In this thesis work for fixed coefficient filter implementation a new memory-based multiplier design is undertaken and deployed in multiplier for basic FIR filter structure and systolic memory-array based FIR filter structure. A new architecture based on approximate distributive arithmetic (DA) computation is introduced for adaptive coefficient implementation of filters. In the first design introduced in this thesis, direct memory-based computing technique is used. Recently, memory-based designs are getting popular because of the advancement in memory technology. Research is proving that memory-based designs are cost effective compared to other designs. Also, memory-based designs are possible for filter design because of the fixed coefficient nature of filters. | |
dc.format.extent | xiv,110 | |
dc.language | English | |
dc.relation | ||
dc.rights | university | |
dc.title | Design and implementation of memory based multipliers for digital filters | |
dc.title.alternative | ||
dc.creator.researcher | Vinitha, C S | |
dc.subject.keyword | Computer Science | |
dc.subject.keyword | Computer Science Information Systems | |
dc.subject.keyword | Engineering and Technology | |
dc.description.note | ||
dc.contributor.guide | Sharma, R. K. | |
dc.publisher.place | Delhi | |
dc.publisher.university | Guru Gobind Singh Indraprastha University | |
dc.publisher.institution | University School of Information and Communication Technology | |
dc.date.registered | 2013 | |
dc.date.completed | 2020 | |
dc.date.awarded | 2022 | |
dc.format.dimensions | 30cm | |
dc.format.accompanyingmaterial | CD | |
dc.source.university | University | |
dc.type.degree | Ph.D. | |
Appears in Departments: | University School of Information and Communication Technology |
Files in This Item:
File | Description | Size | Format | |
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80_recommendation.pdf | Attached File | 1.25 MB | Adobe PDF | View/Open |
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