Design and Analysis of Low Power CMOS Circuits based on Adiabatic Logic

Abstract

This work presents an analysis of various energy recovery approaches based on different adiabatic logic. Various adiabatic logic approaches have been analyzed and compared with different parameters such as the frequency, channel length, supply voltage, and transistor count. Improvements in the adiabatic logic techniques have also been proposed in this work. The first improvement in the CMOS circuits has been achieved using the ultra-low-power diode technique. An adiabatic logic inverter has been proposed using this concept. The reported technique with a combination of ultra-low-power diode and inverter is named as wave shaping diode-based adiabatic logic (WSDAL). Results ix are obtained in 180 nm TSMC technology with a supply voltage of 1.8 V. The proposed inverter shows the power consumption of 0.79 pW with a delay of 52.91 ps with a voltage of 1.8 V. Further a single bit full adder and SR flip-flop circuit are designed using WSDAL and shows the power consumption of 9.29 pW with a delay of 327.72 ps. This adder is designed with 36 transistors. The proposed WSDAL technique is also suitable for designing sequential circuits like SR flip-flops. WSDAL based SR flip-flop consumes a power of 5.45 pW with a delay of 184.80 ps. Another reported work is based on the parallel computation of carry and sum logic in the full-adder circuit. A new design of a single-bit full adder (A-I) is designed in which the input needs to pass only through two MOS transistors and consequently reduces delay time. Another design of a single-bit full adder (A-II)is proposed with two-phase clocked adiabatic static CMOS logic. The third design of a single-bit full adder (A-III) uses parallel logic computation for both sum and carry output. In the adder A-III design, a buffer is used to restore the logic level.