Radiation hardened sram memory design

Abstract

In this era of miniaturization of electronic products, the density of transistors per unit area is increased. Further, increasing power consumption as well as the explosive growth of battery- operated systems on chips - SoCs have made the design of low power circuits, a necessity for future generation VLSI design. There is also a great need to study the effect on performance parameters of the circuit with variations in temperature and voltage. In the past, these variations were not a serious issue, but have become very challenging in the nanoscale regime, due to the increased process variability. newline newlineTechnology scaling leads to the shrinkage of channel length that causes an increase in leakage current hence leakage power dissipation. In this work, a 10T SRAM cell is proposed which used a transistor gating technique to control the leakage current. The stacking effect leads to the low leakage current in the proposed design. The performance of various parameters like write power, write access time, read power, read access time, leakage power, and static noise margin - SNM of proposed 10T SRAM cell is evaluated and compared with the existing designs. Noise margin analysis is done with the N-curve method to observe the stability of the proposed cell. The parametric analysis using Monte Carlo simulation is performed to see the yields and variations of the parameters over 2000 samples. Process corner variation is also carried out to observe its impact on various design metrics. The full custom physical layout is presented to measure area required and its parasitic are extracted to analyze the post-layout simulation for validation. The proposed memory cell shows an improvement in write energy as well in read energy when compared to existing architectures. It also presents the design of 16 x 16 SRAM memory array schematic as well as the physical layout and analyzes the values of various measuring parameters. newline newline