Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/447254
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dc.coverage.spatial
dc.date.accessioned2023-01-16T07:08:23Z-
dc.date.available2023-01-16T07:08:23Z-
dc.identifier.urihttp://hdl.handle.net/10603/447254-
dc.description.abstractAttached
dc.format.extentxvi,134p.
dc.languageEnglish
dc.relation
dc.rightsuniversity
dc.titleLow Drain Induced Barrier Lowering GAAFET for Digital Integrated Circuits
dc.title.alternative
dc.creator.researcherKumar, Amit
dc.subject.keywordEngineering
dc.subject.keywordEngineering and Technology
dc.subject.keywordEngineering Electrical and Electronic
dc.description.note
dc.contributor.guidePattanaik, Manisha and Srivastava, Pankaj
dc.publisher.placeGwalior
dc.publisher.universityAtal Bihari Vajpayee Indian Institute of Information Technology and Management
dc.publisher.institutionDepartment of Electrical and Electronics Engineering
dc.date.registered2015
dc.date.completed2021
dc.date.awarded2022
dc.format.dimensions27.5X21.2
dc.format.accompanyingmaterialDVD
dc.source.universityUniversity
dc.type.degreePh.D.
Appears in Departments:Department of Electrical and Electronics Engineering

Files in This Item:
File Description SizeFormat 
01_title.pdfAttached File31.04 kBAdobe PDFView/Open
02_prelim pages.pdf114.97 kBAdobe PDFView/Open
03_contents.pdf102.92 kBAdobe PDFView/Open
04_abstract.pdf100.83 kBAdobe PDFView/Open
05_chapter 1.pdf309.44 kBAdobe PDFView/Open
06_chapter 2.pdf945.34 kBAdobe PDFView/Open
07_chapter 3.pdf495.17 kBAdobe PDFView/Open
08_chapter 4.pdf515 kBAdobe PDFView/Open
09_chapter 5.pdf486.03 kBAdobe PDFView/Open
10_chapter 6.pdf1.27 MBAdobe PDFView/Open
11_chapter 7.pdf466.53 kBAdobe PDFView/Open
12_annexures.pdf152.29 kBAdobe PDFView/Open
80_recommendation.pdf94.88 kBAdobe PDFView/Open


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