Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/447254
Title: Low Drain Induced Barrier Lowering GAAFET for Digital Integrated Circuits
Researcher: Kumar, Amit
Guide(s): Pattanaik, Manisha and Srivastava, Pankaj
Keywords: Engineering
Engineering and Technology
Engineering Electrical and Electronic
University: Atal Bihari Vajpayee Indian Institute of Information Technology and Management
Completed Date: 2021
Abstract: Attached
Pagination: xvi,134p.
URI: http://hdl.handle.net/10603/447254
Appears in Departments:Department of Electrical and Electronics Engineering

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01_title.pdfAttached File31.04 kBAdobe PDFView/Open
02_prelim pages.pdf114.97 kBAdobe PDFView/Open
03_contents.pdf102.92 kBAdobe PDFView/Open
04_abstract.pdf100.83 kBAdobe PDFView/Open
05_chapter 1.pdf309.44 kBAdobe PDFView/Open
06_chapter 2.pdf945.34 kBAdobe PDFView/Open
07_chapter 3.pdf495.17 kBAdobe PDFView/Open
08_chapter 4.pdf515 kBAdobe PDFView/Open
09_chapter 5.pdf486.03 kBAdobe PDFView/Open
10_chapter 6.pdf1.27 MBAdobe PDFView/Open
11_chapter 7.pdf466.53 kBAdobe PDFView/Open
12_annexures.pdf152.29 kBAdobe PDFView/Open
80_recommendation.pdf94.88 kBAdobe PDFView/Open
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