Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/447237
Title: Highly stable low power and error tolerant SRAM memory design for wireless sensor node and FPGA
Researcher: Sharma, Vishal
Guide(s): Vishvakarma, Santosh Kumar
Keywords: Engineering
Engineering and Technology
Engineering Electrical and Electronic
University: Indian Institute of Technology Indore
Completed Date: 2019
Abstract: Available newline
Pagination: 153p.
URI: http://hdl.handle.net/10603/447237
Appears in Departments:Department of Electrical Engineering

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01_title.pdfAttached File80.73 kBAdobe PDFView/Open
02_prelim pages.pdf261.58 kBAdobe PDFView/Open
03_contents.pdf112.42 kBAdobe PDFView/Open
04_abstract.pdf564.88 kBAdobe PDFView/Open
05_chapter 1.pdf4.96 MBAdobe PDFView/Open
06_chapter 2.pdf1.72 MBAdobe PDFView/Open
07_chapter 3.pdf14.3 MBAdobe PDFView/Open
08_chapter 4.pdf18.02 MBAdobe PDFView/Open
09_chapter 5.pdf29.02 MBAdobe PDFView/Open
10_chapter 6.pdf6.25 MBAdobe PDFView/Open
11_annexure files.pdf260.49 kBAdobe PDFView/Open
80_recommendation.pdf276.21 kBAdobe PDFView/Open
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