Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/445682
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dc.coverage.spatial
dc.date.accessioned2023-01-13T11:43:41Z-
dc.date.available2023-01-13T11:43:41Z-
dc.identifier.urihttp://hdl.handle.net/10603/445682-
dc.description.abstractnewline
dc.format.extentxiii, 67 pages
dc.languageEnglish
dc.relation
dc.rightsuniversity
dc.titleHigh Performance VLSI Architectures for Successive Cancellation Decoding of Polar Codes
dc.title.alternative
dc.creator.researcherJ., Sujanth Roy
dc.subject.keywordEngineering
dc.subject.keywordEngineering and Technology
dc.subject.keywordEngineering Electrical and Electronic
dc.description.note
dc.contributor.guideG., Lakshminarayanan
dc.publisher.placeTiruchirappalli
dc.publisher.universityNational Institute of Technology Tiruchirappalli
dc.publisher.institutionDepartment of Electronics and Communication Engineering
dc.date.registered
dc.date.completed2022
dc.date.awarded2022
dc.format.dimensions
dc.format.accompanyingmaterialNone
dc.source.universityUniversity
dc.type.degreePh.D.
Appears in Departments:Department of Electronics and Communication Engineering

Files in This Item:
File Description SizeFormat 
01_title.pdfAttached File186.45 kBAdobe PDFView/Open
02_prelim.pdf421.32 kBAdobe PDFView/Open
03_content.pdf333.52 kBAdobe PDFView/Open
04_abstract.pdf234.16 kBAdobe PDFView/Open
05_chapter 1.pdf375.58 kBAdobe PDFView/Open
06_chapter 2.pdf791.78 kBAdobe PDFView/Open
07_chapter 3.pdf519.84 kBAdobe PDFView/Open
08_chapter 4.pdf690.06 kBAdobe PDFView/Open
09_chapter 5.pdf849.58 kBAdobe PDFView/Open
10_chapter 6.pdf237.1 kBAdobe PDFView/Open
11_annexures.pdf316.59 kBAdobe PDFView/Open
80_recommendation.pdf274.05 kBAdobe PDFView/Open


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