Shodhganga : a reservoir of Indian theses @ INFLIBNET
The Shodhganga@INFLIBNET Centre provides a platform for research students to deposit their Ph.D. theses and make it available to the entire scholarly community in open access.
Please use this identifier to cite or link to this item:
http://hdl.handle.net/10603/445069
| Title: | Modeling Estimation And Reduction of Total Leakage In Scaled CMOS Logic Circuits |
| Researcher: | Sachdeva, Nitin |
| Guide(s): | Vashishath, Munish and Bansal, PK |
| Keywords: | Engineering Engineering and Technology Engineering Electrical and Electronic |
| University: | J.C. Bose University of Science and Technology, YMCA |
| Completed Date: | 2021 |
| Abstract: | newline |
| Pagination: | |
| URI: | http://hdl.handle.net/10603/445069 |
| Appears in Departments: | Department of Electronics Engineering |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| 01_title.pdf | Attached File | 23.1 kB | Adobe PDF | View/Open |
| 02_prelim pages.pdf | 513.42 kB | Adobe PDF | View/Open | |
| 03_content.pdf | 112.73 kB | Adobe PDF | View/Open | |
| 04_abstract.pdf | 99.45 kB | Adobe PDF | View/Open | |
| 05_chapter 1.pdf | 515.27 kB | Adobe PDF | View/Open | |
| 06_chapter 2.pdf | 191.57 kB | Adobe PDF | View/Open | |
| 07_chapter 3.pdf | 518.44 kB | Adobe PDF | View/Open | |
| 08_chapter 4.pdf | 2.57 MB | Adobe PDF | View/Open | |
| 09_chapter 5.pdf | 531.85 kB | Adobe PDF | View/Open | |
| 10_chapter 6.pdf | 633.8 kB | Adobe PDF | View/Open | |
| 11_chapter 7.pdf | 51.6 kB | Adobe PDF | View/Open | |
| 12_annexures.pdf | 286.86 kB | Adobe PDF | View/Open | |
| 80_recommendation.pdf | 73.7 kB | Adobe PDF | View/Open |
Items in Shodhganga are licensed under Creative Commons Licence Attribution-NonCommercial-ShareAlike 4.0 International (CC BY-NC-SA 4.0).
Altmetric Badge: