Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/444244
Title: Performance enhancement of 3D cylindrical gate all around tunnel FET and its applications for ultra low power cross coupled voltage doubler circuit design
Researcher: Beohar, Ankur
Guide(s): Vishvakarma, Santosh Kumar
Keywords: Engineering
Engineering and Technology
Engineering Electrical and Electronic
University: Indian Institute of Technology Indore
Completed Date: 2019
Abstract: Available newline
Pagination: 116p.
URI: http://hdl.handle.net/10603/444244
Appears in Departments:Department of Electrical Engineering

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01_title.pdfAttached File74.64 kBAdobe PDFView/Open
02_prelim pages.pdf351.17 kBAdobe PDFView/Open
03_contents.pdf159.24 kBAdobe PDFView/Open
04_abstract.pdf80.88 kBAdobe PDFView/Open
05_chapter 1.pdf1.01 MBAdobe PDFView/Open
06_chapter 2.pdf855.58 kBAdobe PDFView/Open
07_chapter 3.pdf1.45 MBAdobe PDFView/Open
08_chapter 4.pdf390.59 kBAdobe PDFView/Open
09_chapter 5.pdf956.04 kBAdobe PDFView/Open
10_annexure files.pdf257.93 kBAdobe PDFView/Open
80_recommendation.pdf241.24 kBAdobe PDFView/Open
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