Please use this identifier to cite or link to this item:
http://hdl.handle.net/10603/443413
Title: | Analytical Modeling and Simulation of Some Gate Source Structure Engineered Cylindrical Gate Tunnel FETs |
Researcher: | Singh, Prince Kumar |
Guide(s): | Jit, Satyabrata |
Keywords: | Engineering Engineering and Technology Engineering Electrical and Electronic |
University: | Indian Institute of Technology IIT (BHU), Varanasi |
Completed Date: | 2020 |
Abstract: | newlineAbstract is available in the content |
Pagination: | xxx, 157 |
URI: | http://hdl.handle.net/10603/443413 |
Appears in Departments: | Electronics Engineering |
Files in This Item:
File | Description | Size | Format | |
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01_title page.pdf | Attached File | 242.2 kB | Adobe PDF | View/Open |
02_priliminary page.pdf | 463.9 kB | Adobe PDF | View/Open | |
03_content page.pdf | 885.23 kB | Adobe PDF | View/Open | |
04_abstrct.pdf | 222.86 kB | Adobe PDF | View/Open | |
05_chapter_01.pdf | 1.36 MB | Adobe PDF | View/Open | |
06_chapter_02.pdf | 1.45 MB | Adobe PDF | View/Open | |
07_chapter_03.pdf | 1.29 MB | Adobe PDF | View/Open | |
08_chapter_04.pdf | 1.38 MB | Adobe PDF | View/Open | |
09_chapter_05.pdf | 482.6 kB | Adobe PDF | View/Open | |
10_anuxure.pdf | 411.06 kB | Adobe PDF | View/Open | |
80_recommendation.pdf | 631.67 kB | Adobe PDF | View/Open |
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