1. Shodhganga@INFLIBNET
  2. Indian Institute of Technology IIT (BHU), Varanasi
  3. Electronics Engineering
Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/443413
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DC FieldValueLanguage
dc.coverage.spatial
dc.date.accessioned2023-01-12T06:47:00Z-
dc.date.available2023-01-12T06:47:00Z-
dc.identifier.urihttp://hdl.handle.net/10603/443413-
dc.description.abstractnewlineAbstract is available in the content
dc.format.extentxxx, 157
dc.languageEnglish
dc.relation
dc.rightsuniversity
dc.titleAnalytical Modeling and Simulation of Some Gate Source Structure Engineered Cylindrical Gate Tunnel FETs
dc.title.alternative
dc.creator.researcherSingh, Prince Kumar
dc.subject.keywordEngineering
dc.subject.keywordEngineering and Technology
dc.subject.keywordEngineering Electrical and Electronic
dc.description.note
dc.contributor.guideJit, Satyabrata
dc.publisher.placeVaranasi
dc.publisher.universityIndian Institute of Technology IIT (BHU), Varanasi
dc.publisher.institutionElectronics Engineering
dc.date.registered2015
dc.date.completed2020
dc.date.awarded2020
dc.format.dimensions
dc.format.accompanyingmaterialDVD
dc.source.universityUniversity
dc.type.degreePh.D.
Appears in Departments:Electronics Engineering

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01_title page.pdfAttached File242.2 kBAdobe PDFView/Open
02_priliminary page.pdf463.9 kBAdobe PDFView/Open
03_content page.pdf885.23 kBAdobe PDFView/Open
04_abstrct.pdf222.86 kBAdobe PDFView/Open
05_chapter_01.pdf1.36 MBAdobe PDFView/Open
06_chapter_02.pdf1.45 MBAdobe PDFView/Open
07_chapter_03.pdf1.29 MBAdobe PDFView/Open
08_chapter_04.pdf1.38 MBAdobe PDFView/Open
09_chapter_05.pdf482.6 kBAdobe PDFView/Open
10_anuxure.pdf411.06 kBAdobe PDFView/Open
80_recommendation.pdf631.67 kBAdobe PDFView/Open
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