Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/443413
Title: Analytical Modeling and Simulation of Some Gate Source Structure Engineered Cylindrical Gate Tunnel FETs
Researcher: Singh, Prince Kumar
Guide(s): Jit, Satyabrata
Keywords: Engineering
Engineering and Technology
Engineering Electrical and Electronic
University: Indian Institute of Technology IIT (BHU), Varanasi
Completed Date: 2020
Abstract: newlineAbstract is available in the content
Pagination: xxx, 157
URI: http://hdl.handle.net/10603/443413
Appears in Departments:Electronics Engineering

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80_recommendation.pdf631.67 kBAdobe PDFView/Open
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