Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/442323
Title: Development of High Performance Hardware Architectures for Optimized Motion Estimation Algorithms for High Efficiency Video Coding
Researcher: Gogoi, Sushanta
Guide(s): Rangababu, P.
Keywords: Efficiency Video Coding
Estimation Algorithms
Hardware Architectures
University: National Institute of Technology (NIT) Meghalaya
Completed Date: 2022
Abstract: Available
Pagination: xviii,124p.
URI: http://hdl.handle.net/10603/442323
Appears in Departments:ELECTRONICS & COMMUNICATION ENGINEERING

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01_title.pdfAttached File37.11 kBAdobe PDFView/Open
02_prelim pages.pdf445.14 kBAdobe PDFView/Open
03_content.pdf103.91 kBAdobe PDFView/Open
04_abstract.pdf78.43 kBAdobe PDFView/Open
05_chapter 1.pdf809.03 kBAdobe PDFView/Open
06_chapter 2.pdf1.18 MBAdobe PDFView/Open
07_chapter 3.pdf576.91 kBAdobe PDFView/Open
08_chapter 4.pdf5.23 MBAdobe PDFView/Open
09_chapter 5.pdf17.43 MBAdobe PDFView/Open
10_chapter 6.pdf4.86 MBAdobe PDFView/Open
11_chapter 7.pdf140.29 kBAdobe PDFView/Open
12_annexures.pdf215.28 kBAdobe PDFView/Open
80_recommendation.pdf176.24 kBAdobe PDFView/Open
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