SoC Design Space Exploration for High Level Synthesis

Abstract

FPGAs are increasing the adoption for accelerating computations in high-performance computing, especially in the domains that demand power and energy efficiency. FPGA s flexible architecture provides various optimization opportunities in terms of providing highly parallel architecture and fine-grained pipelining. However this flexibility comes with a challenge of complex hardware programming. Designing an RTL (Register Transfer Level) code is error prone and requires programmers to have detailed hardware knowledge in terms of architecture-specific parameters such as the LUTs (Look-Up Tables), DSPs (Digital Signal Processors) and BRAMs (Block Random Access Memories). Writing hardware code is time consuming as compared to writing a corresponding software code. High-Level Synthesis (HLS) addresses these problems by enabling software designers to efficiently design hardware using their choice of high-level language such as C, C++, SystemC, CUDA and translating this code to hardware language such as Verilog or VHDL, without much insight into the underlying architecture. It promises shorter hardware design time with improved performance and energy efficiency. HLS also benefits hardware designers by providing a high level of abstraction and rapid design space exploration to design system faster. The acquisition of Altera by Intel, Xilinx by AMD, as well as Microsoft s initiative to use FPGAs in their Bing search acceleration is a clear indication to focus on design methodologies for software to be executed on FPGAs. Various applications in the domain of machine learning, medical image processing, and neural networks have utilized HLS for significant benefits in terms of performance and energy consumption. newlineHLS tools also allow programmers to influence hardware design settings via various pragmas or synthesis directives. For example, the programmer is able to choose whether an array variable is to be mapped to a register or memory, whether a function is to be implemented as an inline function or not, the amount of unroll