Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/435501
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DC FieldValueLanguage
dc.coverage.spatial
dc.date.accessioned2023-01-03T10:58:59Z-
dc.date.available2023-01-03T10:58:59Z-
dc.identifier.urihttp://hdl.handle.net/10603/435501-
dc.description.abstractnewline
dc.format.extent
dc.languageEnglish
dc.relation
dc.rightsuniversity
dc.titlelow power design for combinational and sequential multi valued logics using carbon nano tube transistors
dc.title.alternative
dc.creator.researcherLatha A
dc.subject.keywordEngineering
dc.subject.keywordEngineering and Technology
dc.subject.keywordEngineering Electrical and Electronic
dc.description.note
dc.contributor.guideYamuna G
dc.publisher.placeAnnamalai Nagar
dc.publisher.universityAnnamalai University
dc.publisher.institutionDepartment of Electronics and Communication Engineering
dc.date.registered2016
dc.date.completed2022
dc.date.awarded2022
dc.format.dimensions
dc.format.accompanyingmaterialDVD
dc.source.universityUniversity
dc.type.degreePh.D.
Appears in Departments:Department of Electronics & Communication Engineering

Files in This Item:
File Description SizeFormat 
12.chapter 5.pdfAttached File619.8 kBAdobe PDFView/Open
14.chapter 7.pdf182.21 kBAdobe PDFView/Open
2. declaration.pdf152.91 kBAdobe PDFView/Open
3. certificate.pdf205.04 kBAdobe PDFView/Open
4. acknowledgement.pdf150.07 kBAdobe PDFView/Open
80_recommendation.pdf182.21 kBAdobe PDFView/Open
8. chapter 1.pdf550.49 kBAdobe PDFView/Open
9. chapter 2.pdf450.35 kBAdobe PDFView/Open


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