1. Shodhganga@INFLIBNET
  2. Indian Institute of Technology Delhi
  3. Department of Electrical Engineering
Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/433659
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DC FieldValueLanguage
dc.coverage.spatialElectrical Engineering
dc.date.accessioned2022-12-29T10:44:12Z-
dc.date.available2022-12-29T10:44:12Z-
dc.identifier.urihttp://hdl.handle.net/10603/433659-
dc.description.abstractAbstract Available
dc.format.extent
dc.languageEnglish
dc.relationTH-5830
dc.rightsuniversity
dc.titleCmos scaling considerations in sub 10 nm node multiple gate fets
dc.title.alternativeNa
dc.creator.researcherBansal, Anil Kumar
dc.subject.keywordEngineering
dc.subject.keywordEngineering and Technology
dc.subject.keywordEngineering Electrical and Electronic
dc.description.note
dc.contributor.guideDixit, Abhisek
dc.publisher.placeDelhi
dc.publisher.universityIndian Institute of Technology Delhi
dc.publisher.institutionDepartment of Electrical Engineering
dc.date.registered
dc.date.completed2019
dc.date.awarded2019
dc.format.dimensions
dc.format.accompanyingmaterialDVD
dc.source.universityUniversity
dc.type.degreePh.D.
Appears in Departments:Department of Electrical Engineering

Files in This Item:
File Description SizeFormat 
01_title.pdfAttached File122.75 kBAdobe PDFView/Open
02_prelim pages.pdf2.14 MBAdobe PDFView/Open
03_content.pdf280.93 kBAdobe PDFView/Open
04_abstract.pdf686.26 kBAdobe PDFView/Open
05_chapter 1.pdf3.39 MBAdobe PDFView/Open
06_chapter 2.pdf2.89 MBAdobe PDFView/Open
07_chapter 3.pdf3.02 MBAdobe PDFView/Open
08_chapter 4.pdf4.53 MBAdobe PDFView/Open
09_chapter 5.pdf6.1 MBAdobe PDFView/Open
10_chapter 6.pdf5.61 MBAdobe PDFView/Open
11_chapter 7.pdf726.43 kBAdobe PDFView/Open
12_annexures.pdf1.46 MBAdobe PDFView/Open
80_recommendation.pdf780.01 kBAdobe PDFView/Open
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