Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/433659
Title: Cmos scaling considerations in sub 10 nm node multiple gate fets
Researcher: Bansal, Anil Kumar
Guide(s): Dixit, Abhisek
Keywords: Engineering
Engineering and Technology
Engineering Electrical and Electronic
University: Indian Institute of Technology Delhi
Completed Date: 2019
Abstract: Abstract Available
Pagination: 
URI: http://hdl.handle.net/10603/433659
Appears in Departments:Department of Electrical Engineering

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01_title.pdfAttached File122.75 kBAdobe PDFView/Open
02_prelim pages.pdf2.14 MBAdobe PDFView/Open
03_content.pdf280.93 kBAdobe PDFView/Open
04_abstract.pdf686.26 kBAdobe PDFView/Open
05_chapter 1.pdf3.39 MBAdobe PDFView/Open
06_chapter 2.pdf2.89 MBAdobe PDFView/Open
07_chapter 3.pdf3.02 MBAdobe PDFView/Open
08_chapter 4.pdf4.53 MBAdobe PDFView/Open
09_chapter 5.pdf6.1 MBAdobe PDFView/Open
10_chapter 6.pdf5.61 MBAdobe PDFView/Open
11_chapter 7.pdf726.43 kBAdobe PDFView/Open
12_annexures.pdf1.46 MBAdobe PDFView/Open
80_recommendation.pdf780.01 kBAdobe PDFView/Open
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