1. Shodhganga@INFLIBNET
  2. National Institute of Technology (NIT), Warangal
  3. Department of Electronics and Communication Engineering
Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/433113
Title: Some Investigations on Efficient Testing Fault Diagnosis Algorithms for VLSI Circuits
Researcher: Rayudu, K V B V
Guide(s): Rao, P Sreehari and Jahagirdar, D R
Keywords: Efficient Testing
Engineering
Engineering and Technology
Engineering Electrical and Electronic
Fault Diagnosis
VLSI Circuits
University: National Institute of Technology Warangal
Completed Date: 2022
Abstract: Attached
Pagination: xvi, 78p.
URI: http://hdl.handle.net/10603/433113
Appears in Departments:Department of Electronics and Communication Engineering

Files in This Item:
File Description SizeFormat 
01_title.pdfAttached File98.62 kBAdobe PDFView/Open
02_declaration.pdf52.02 kBAdobe PDFView/Open
03_certificate.pdf61.6 kBAdobe PDFView/Open
04_acknowledgement.pdf53.74 kBAdobe PDFView/Open
05_abstract.pdf69.8 kBAdobe PDFView/Open
06_content.pdf53.24 kBAdobe PDFView/Open
07_list of tables and figures.pdf67.8 kBAdobe PDFView/Open
08_abbreviations.pdf79.11 kBAdobe PDFView/Open
09_chapter 1.pdf61.72 kBAdobe PDFView/Open
10_chapter 2.pdf341.03 kBAdobe PDFView/Open
11_chapter 3.pdf1.67 MBAdobe PDFView/Open
12_chapter 4.pdf3.24 MBAdobe PDFView/Open
13_chapter 5.pdf65.93 kBAdobe PDFView/Open
14_bibliography.pdf132.8 kBAdobe PDFView/Open
80_recommendation.pdf149.69 kBAdobe PDFView/Open
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