Vlsi implementation of high speed arithmetic blocks using vedic mathematics

Abstract

The development in Very Large-Scale Integration (VLSI) newlinetechnology demands a greater number of functionalities in a single IC. newlinePortable computing and personal communication applications such as newlinenotebook computers, laptops, and mobiles demand high speed, low delay and newlinereduced power dissipation. To meet the required parameter such as speed, newlinedelay and power, Vedic mathematics is applied in signal processing newlineapplications. newlineJagadguru Shri Bharathi Krishna Tirthaji discovered the ancient newlinesystem of mathematics called Vedic mathematics. Vedic mathematics is newlinederived from Vedas, and it is composed of 16 sutras and 13 sub-sutras which newlinesolve mathematics arithmetic, geometry, calculus conics and algebra. Solving newlineproblem by conventional mathematical steps in modern mathematics is more newlinecomplex and time-consuming. Vedic mathematics is used to solve newlinemathematical problems in a fast manner by doing mental calculation itself. newlineVedic aphorisms can be used in the implementation of fast newlinealgorithms in various fields of engineering. In Digital signal processors newlinemultiply and accumulate is the basic functional unit. High speed, low delay newlinemultipliers are designed to reduce the computational complexity. The Vedic newlinemultiplier is better compared with conventional multiplier based on the newlineparameters such as speed, delay area, power, regularity of structure and its newlinelayout. Vedic Arithmetic logical unit (ALU) is designed by using various newlinearithmetic operations by using different sutras. Vedic ALU is composed of newlinearithmetic operation newline