Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/430675
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dc.coverage.spatial
dc.date.accessioned2022-12-24T05:15:46Z-
dc.date.available2022-12-24T05:15:46Z-
dc.identifier.urihttp://hdl.handle.net/10603/430675-
dc.description.abstractThe abstract is available in the attachment. newline
dc.format.extentxxxvi,164
dc.languageEnglish
dc.relation
dc.rightsuniversity
dc.titleTCAD Simulation Based Device and Circuit Level Performance Analysis of Source Pocket Engineered GaSb Si Heterojunction Vertical TFETs
dc.title.alternative
dc.creator.researcherTripathy, Manas Ranjan
dc.subject.keywordEngineering
dc.subject.keywordEngineering and Technology
dc.subject.keywordEngineering Electrical and Electronic
dc.description.note
dc.contributor.guideJit, Satyabrata
dc.publisher.placeVaranasi
dc.publisher.universityIndian Institute of Technology IIT (BHU), Varanasi
dc.publisher.institutionElectronics Engineering
dc.date.registered2017
dc.date.completed2020
dc.date.awarded2020
dc.format.dimensions
dc.format.accompanyingmaterialDVD
dc.source.universityUniversity
dc.type.degreePh.D.
Appears in Departments:Electronics Engineering

Files in This Item:
File Description SizeFormat 
01_title page.pdfAttached File1.84 MBAdobe PDFView/Open
02_preliminary page.pdf5.76 MBAdobe PDFView/Open
03_content.pdf4.32 MBAdobe PDFView/Open
04_abstract.pdf1.22 MBAdobe PDFView/Open
05_chapter 01.pdf15.36 MBAdobe PDFView/Open
06_chapter 02.pdf14.44 MBAdobe PDFView/Open
07_chapter 03.pdf8.75 MBAdobe PDFView/Open
08_chapter 04.pdf5.69 MBAdobe PDFView/Open
09_chapter 05.pdf5.28 MBAdobe PDFView/Open
10_chapter 06.pdf1.23 MBAdobe PDFView/Open
11_annexure.pdf5.99 MBAdobe PDFView/Open
80_recommendation.pdf3.07 MBAdobe PDFView/Open


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