Please use this identifier to cite or link to this item:
http://hdl.handle.net/10603/429877
Title: | Low Power Machine Learning Systems for Energy Efficient Edge Devices |
Researcher: | Nair, Abhishek Ramdas |
Guide(s): | Thakur, Chetan Singh |
Keywords: | Engineering Engineering and Technology Engineering Electrical and Electronic |
University: | Indian Institute of Science Bangalore |
Completed Date: | 2021 |
Abstract: | Energy-efficient devices are essential in the world of edge computing and the tiny Machine Learning (tinyML) paradigm. Edge devices are often constrained by the available compu- tational power and hardware resource. To this end, there is a need for systems to implement low-power designs for machine learning at the edge. This research aims at designing edge device deployable low power frameworks honouring the hardware constraints. One such novel system is presented here as an in-filter computing framework that can be used for designing ultra-light classifiers for time-series data. Unlike a conventional pattern recognizer, where the feature extraction and classification are designed independently, this architecture integrates the convo- lution and nonlinear filtering operations directly into the kernels of a Support Vector Machine (SVM). The result of this integration is a template-based SVM whose memory and computa- tional footprint (training and inference) are light enough to be implemented on a constrained IoT platform like microcontrollers or Field Programmable Gate Array (FPGA)-based systems. Template-based SVM do not impose restriction on the SVM kernel to be positive-definite and allows the user to define memory constraint in terms of fixed template vectors. This makes the framework scalable and enables its implementation for low-power, high-density and memory constrained embedded application. Low power computation on resource constrained devices can also be achieved at the implementation level using approximate computing. Multiply- Accumulate (MAC) is one of the most common operations in any design. Multiplication con- sumes more area and power compared to other basic operations. Hence, a novel framework is developed which approximates the multiplication operation to create a multiplierless design. This multiplierless classification framework uses a piecewise linear (PWL) approximation based on a margin propagation (MP) technique and uses only addition/subtraction, shift, compari- son,... |
Pagination: | xvi, 139 |
URI: | http://hdl.handle.net/10603/429877 |
Appears in Departments: | Electronic Systems Engineering |
Files in This Item:
File | Description | Size | Format | |
---|---|---|---|---|
01_title.pdf | Attached File | 169.98 kB | Adobe PDF | View/Open |
02_prelim pages.pdf | 217.48 kB | Adobe PDF | View/Open | |
03_table of content.pdf | 51.93 kB | Adobe PDF | View/Open | |
04_abstract.pdf | 48.33 kB | Adobe PDF | View/Open | |
05_chapter 1.pdf | 3.87 MB | Adobe PDF | View/Open | |
06_chapter 2.pdf | 1.25 MB | Adobe PDF | View/Open | |
07_chapter 3.pdf | 1.06 MB | Adobe PDF | View/Open | |
08_chapter 4.pdf | 1.32 MB | Adobe PDF | View/Open | |
09_chapter 5.pdf | 641.8 kB | Adobe PDF | View/Open | |
10_chapter 6.pdf | 788.43 kB | Adobe PDF | View/Open | |
11_annexure.pdf | 353.88 kB | Adobe PDF | View/Open | |
80_recommendation.pdf | 265.18 kB | Adobe PDF | View/Open |
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