Please use this identifier to cite or link to this item:
http://hdl.handle.net/10603/428526
Title: | Hardware architectures for accelerating convolution operations in convolutional neural network |
Researcher: | Hazarika, Anakhi |
Guide(s): | Poddar, Soumyajit |
Keywords: | Engineering Engineering and Technology Engineering Electrical and Electronic Hardware Accelerator, Convolutional Neural Network, FPGA, Approximate Computing, Machine Learning |
University: | Indian Institute of Information Technology Guwahati |
Completed Date: | 2022 |
Abstract: | newline |
Pagination: | xx,137p. |
URI: | http://hdl.handle.net/10603/428526 |
Appears in Departments: | Electronics and Communication Engineering |
Files in This Item:
File | Description | Size | Format | |
---|---|---|---|---|
01_title.pdf | Attached File | 58.17 kB | Adobe PDF | View/Open |
02_prelim pages.pdf | 2.21 MB | Adobe PDF | View/Open | |
03_abstract.pdf | 87.19 kB | Adobe PDF | View/Open | |
04_content.pdf | 111.75 kB | Adobe PDF | View/Open | |
05_chapter 1.pdf | 3.97 MB | Adobe PDF | View/Open | |
06_chapter 2.pdf | 5.27 MB | Adobe PDF | View/Open | |
07_chapter 3.pdf | 7.08 MB | Adobe PDF | View/Open | |
08_chapter 4.pdf | 2.2 MB | Adobe PDF | View/Open | |
09_chapter 5.pdf | 96.87 kB | Adobe PDF | View/Open | |
10_annexures.pdf | 220.56 kB | Adobe PDF | View/Open | |
80_recommendation.pdf | 154.54 kB | Adobe PDF | View/Open |
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