Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/428526
Title: Hardware architectures for accelerating convolution operations in convolutional neural network
Researcher: Hazarika, Anakhi
Guide(s): Poddar, Soumyajit
Keywords: Engineering
Engineering and Technology
Engineering Electrical and Electronic
Hardware Accelerator, Convolutional Neural Network, FPGA, Approximate Computing, Machine Learning 
University: Indian Institute of Information Technology Guwahati
Completed Date: 2022
Abstract: newline
Pagination: xx,137p.
URI: http://hdl.handle.net/10603/428526
Appears in Departments:Electronics and Communication Engineering

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01_title.pdfAttached File58.17 kBAdobe PDFView/Open
02_prelim pages.pdf2.21 MBAdobe PDFView/Open
03_abstract.pdf87.19 kBAdobe PDFView/Open
04_content.pdf111.75 kBAdobe PDFView/Open
05_chapter 1.pdf3.97 MBAdobe PDFView/Open
06_chapter 2.pdf5.27 MBAdobe PDFView/Open
07_chapter 3.pdf7.08 MBAdobe PDFView/Open
08_chapter 4.pdf2.2 MBAdobe PDFView/Open
09_chapter 5.pdf96.87 kBAdobe PDFView/Open
10_annexures.pdf220.56 kBAdobe PDFView/Open
80_recommendation.pdf154.54 kBAdobe PDFView/Open
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