Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/427659
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dc.coverage.spatialSpeed power and area efficient Design of multiplier and adder For 2d fir digital filter
dc.date.accessioned2022-12-18T09:55:15Z-
dc.date.available2022-12-18T09:55:15Z-
dc.identifier.urihttp://hdl.handle.net/10603/427659-
dc.description.abstractSpeed power and area efficient Design of multiplier and adder For 2d fir digital filter newline
dc.format.extentxv, 130p.
dc.languageEnglish
dc.relationp.122-129
dc.rightsuniversity
dc.titleSpeed power and area efficient Design of multiplier and adder For 2d fir digital filter
dc.title.alternative
dc.creator.researcherDyana christilda, V
dc.subject.keywordEngineering and Technology
dc.subject.keywordEngineering
dc.subject.keywordEngineering Electrical and Electronic
dc.description.note
dc.contributor.guide
dc.publisher.placeChennai
dc.publisher.universityAnna University
dc.publisher.institutionFaculty of Information and Communication Engineering
dc.date.registered
dc.date.completed2022
dc.date.awarded2022
dc.format.dimensions21cm
dc.format.accompanyingmaterialNone
dc.source.universityUniversity
dc.type.degreePh.D.
Appears in Departments:Faculty of Information and Communication Engineering

Files in This Item:
File Description SizeFormat 
01_title.pdfAttached File117.8 kBAdobe PDFView/Open
02_prelim pages.pdf1.38 MBAdobe PDFView/Open
03_content.pdf108.88 kBAdobe PDFView/Open
04_abstract.pdf179.84 kBAdobe PDFView/Open
05_chapter 1.pdf441.37 kBAdobe PDFView/Open
06_chapter 2.pdf290.5 kBAdobe PDFView/Open
07_chapter 3.pdf706.95 kBAdobe PDFView/Open
08_chapter 4.pdf422.48 kBAdobe PDFView/Open
09_chapter 5.pdf353.53 kBAdobe PDFView/Open
10_chapter 6.pdf487.02 kBAdobe PDFView/Open
11_annexures.pdf462.96 kBAdobe PDFView/Open
80_recommendation.pdf74.49 kBAdobe PDFView/Open


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