A systematic design of novel energy efficient 64 bit parallel prefix adder

Abstract

The very large scale integration technology (VLSI) is extensively used in the most of the emerging field like telecommunication, signal processing, consumer electronics and instrumentation etc. The integration complexities in integrated circuits doubled in every one and half year as per the Moore s law. Over the period of time, there is a magnificent increase in integration density and computational complexity in digital integrated circuit design. This impact created the advances in technology scaling, where in device sizes are continuously scaled down. But continuous technology scaling and device miniaturization affect the operational characteristics and device property that in turn affect the trust worthy operation of the VLSI systems. The CMOS technology offers the most impressive performance than the other device technologies for the VLSI system and its computations. The advancement of CMOS technology created the newer interest in the design of the fundamental adder units in the digital system. Even the technology scaling not achieves the constant power density, the energy efficiency of the functional units very important and major design challenge for the system designers. newlineThe challenges involved in the development of telecommunication, signal processing, consumer electronics and instrumentation etc, demand the need for the design of low power and energy efficient VLSI systems. In a decade earlier, in VLSI design primary focus on optimizing speed and area and secondary importance is given for power newline