Design of a novel filter on electromyogram signal using m tree structure multiplier

Abstract

In this contemporary world, Very Large Scale Integrated circuits newline(VLSI) have a significant aspect of improving circuit efficiency. Different levels newlineof design process had been labeled in VLSI techniques such as System-Level newlineDesign, Architecture or Algorithm Level Design, Digital System Level Design, newlineLogical Level Design, Electrical Level Design, Layout Level Design, and newlineSemiconductor Level design. This area of research focused on low power VLSI newlinedesign to improve system efficiency. The proposed circuit depends on newlineconventional and pipeline design techniques with sophisticated design tools, newlinewhich have been used to increase the system speed, reduce the power, and newlineprocessing time. This method precedes a novel digital circuit design by using the newlineproposed adder, multiplier, and digital filter. The overall system visualization is newlineused to increase the performance of a digital circuit. newlineIn any digital circuit design, an adder is the base function to expand the newlinenetwork system, the key function of an adder is used to produce the sum and carry. newlineIn this research, a modified carry save adder has been designed and compared with newlineother conventional and pipeline adder s. The contribution of a carry save adder is newlineused to save the carry signal between all the segments of the digital circuit to newlineminimize the delay and reduce circuit complexity. The specialty of carry save newlineadder has a simple and easiest design process, when increasing the network band newlinethe carry save adder has been produced with less delay. In this research, the newlineproposed carry save adder is classified into two categories, the first one is a newlinemodified carry save adder and another one is the majority carry save adder. The newlinedesign of the proposed pipeline carry save 16-bit adders has to produce an newlineoptimum result by using Xilinx ISE 14.7 and Modelsim Altera 10.1 d simulation newline