Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/424620
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dc.coverage.spatialCertain investigations on the Performance improvement in virtual Secure circuit with dvanced Encryption standard for Cryptographic processor
dc.date.accessioned2022-12-12T08:23:14Z-
dc.date.available2022-12-12T08:23:14Z-
dc.identifier.urihttp://hdl.handle.net/10603/424620-
dc.description.abstractSecuring embedded systems not only require the security newlineprotocols and cryptographic algorithms, but also the security newlineimplementations. The data that are encrypted for secure transmission are newlinethreatened by various attacks. One among them is a Side Channel Attack newline(SCA) which breaks the cryptographic implementation within few hours newlineresulting in a threat to embedded systems. This threat is overcome by an newlinealgorithm independent Virtual Secure Circuit (VSC), which is used as a newlinesoftware countermeasure to obviate the problem of SCA. Further the newlinecomputation is processed by VSC with Advanced Encryption Standard newline(AES) to analyse its performance in terms of delay and throughput in Field newlineProgrammable Gate Array (FPGA) implementation. Though it thwarts the newlineattacks, the parameters like delay and throughput are not as efficient as newlineexpected in the implementation of VSC with AES. For improving the newlineperformance of VSC with AES, a Fully Parallel Pipelined Architecture has newlinebeen used to provide less delay and high throughput. The usage of resource newlinesharing architecture and gate replacement methods in Mix-column techniques newlinehelps to improve data reliability during transmission using TCP/IP protocol newlinesuite and reduces the area utilisation and power consumption. To relatively newlinereduce the power consumption a different method of SBox optimization is newlineused in network. newlineThis method is proposed with AES to provide the security and quality newlineof transmission in various areas like hospitals and military application. The newlineresults show performance improvement and optimisation of various newlineparameters like Area Utilisation, Power consumption, Throughput, Delay and newlineMaximum Frequency of Operation when compared with VSC with AES newlinesystems. newline
dc.format.extentxvii, 139p.
dc.languageEnglish
dc.relationp.128-138
dc.rightsuniversity
dc.titleCertain investigations on the Performance improvement in virtual Secure circuit with dvanced Encryption standard for Cryptographic processor
dc.title.alternative
dc.creator.researcherMadhavapandian, S
dc.subject.keywordEngineering and Technology
dc.subject.keywordEngineering
dc.subject.keywordEngineering Electrical and Electronic
dc.subject.keywordvirtual Secure circuit
dc.subject.keywordCryptographic processor
dc.description.note
dc.contributor.guideMaruthupandi, P
dc.publisher.placeChennai
dc.publisher.universityAnna University
dc.publisher.institutionFaculty of Electrical Engineering
dc.date.registered
dc.date.completed2021
dc.date.awarded2021
dc.format.dimensions21cm
dc.format.accompanyingmaterialNone
dc.source.universityUniversity
dc.type.degreePh.D.
Appears in Departments:Faculty of Electrical Engineering

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01_title.pdfAttached File63.9 kBAdobe PDFView/Open
02_prelim pages.pdf2.14 MBAdobe PDFView/Open
03_content.pdf90.61 kBAdobe PDFView/Open
04_abstract.pdf59.77 kBAdobe PDFView/Open
05_chapter 1.pdf562.11 kBAdobe PDFView/Open
06_chapter 2.pdf301.84 kBAdobe PDFView/Open
07_chapter 3.pdf644.53 kBAdobe PDFView/Open
08_chapter 4.pdf388.43 kBAdobe PDFView/Open
09_chapter 5.pdf346.35 kBAdobe PDFView/Open
10_chapter 6.pdf121.61 kBAdobe PDFView/Open
11_chapter 7.pdf103.4 kBAdobe PDFView/Open
12_annexures.pdf339.64 kBAdobe PDFView/Open
80_recommendation.pdf166.39 kBAdobe PDFView/Open


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