Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/422154
Title: Test pattern generation and fault localization for some fault models in reversible circuits
Researcher: Handique, Mousum
Guide(s): Deka, Jantindra Kumar and Biswas, Santosh
Keywords: Computer Science
Computer Science Hardware and Architecture
Engineering and Technology
University: Indian Institute of Technology Guwahati
Completed Date: 2020
Abstract: In this thesis we consider some of the fault models to generate the test patterns to detect these faults in reversible circuits In the first phase of our work we consider the bridging faults at the input level We identify a test set to detect all possible input bridging faults in a reversible circuit and establish that the test set is minimal and complete It is also indicated that by adding one particular test vector to this test set input stuckat fault can also be detectedIn the next wo newline newline
Pagination: 
URI: http://hdl.handle.net/10603/422154
Appears in Departments:Department of Computer Science and Engineering

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