An efficient FPGA architecture based on hybrid logic blocks and performance enhancement of FPGA using placement and routing algorithms

Abstract

As per Moore s law the number of transistors on a chip doubles every two years and the growth follows an exponential curve in the past decade Field Programmable Gate Arrays FPGAs are a reliable choice of implementation platform for digital circuits The higher density of the transistors on the FPGA creates new challenges for researchers in this field The performance in terms of speed area and power became more important for producing the desired quality of results on the high density FPGAs The functionality of the digital circuits implemented on the FPGAs is synthesized and mapped onto the logic elements of the logic blocks on the FPGA architecture The effectiveness and reliability of logic elements to realize the intended logic functions of the circuit is a key parameter for the performance of FPGA Hence the performances of FPGAs are significantly influenced by an efficient design of logic blocks and the quality of suitable placement and routing algorithms used for mapping the logic blocks on the FPGAs for the functional description of digital circuits This research work focuses on enhancing the performance of FPGAs using a hybrid design of logic blocks and the development of placement and routing algorithms to implement the various digital circuits on the FPGAs The first research work analyses various logic elements such as Look Up Tables LUTs and Universal Logic Gates ULGs required in the design of logic blocks with their performances and ULGs are found to be efficient candidates for the design of logic blocks on the FPGA ULG is used along with the LUT to realize all classes of Negation Permutation Negation NPN equivalent logic functions in an efficient manner newline