1. Shodhganga@INFLIBNET
  2. Indian Institute of Technology Guwahati
  3. Department of Computer Science and Engineering
Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/421166
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DC FieldValueLanguage
dc.coverage.spatialComputer Science and Engineering
dc.date.accessioned2022-11-29T12:59:46Z-
dc.date.available2022-11-29T12:59:46Z-
dc.identifier.urihttp://hdl.handle.net/10603/421166-
dc.description.abstractThe ever increasing demand for higher processing speed with hiked data parallelism force the computer architects to increase the number of processing cores on a single chip called Chip Multi processors CMPs Towards meeting the performance goals these CMPs are equipped with larger on chip Last Level Caches LLCs to enhance the probability of the presence of data on chip during process execution The existing literature portrays that conventional LLCs built in charge based memory technologies...
dc.format.extentNot Available
dc.languageEnglish
dc.relationNot Available
dc.rightsself
dc.titleLinovo longevity enhancement of non volatile caches by placement write restriction and victim caching in chip multi processors
dc.title.alternativeNot available
dc.creator.researcherAgarwal, Sukarn
dc.subject.keywordComputer Science
dc.subject.keywordComputer Science Artificial Intelligence
dc.subject.keywordEngineering and Technology
dc.description.noteNot Available
dc.contributor.guideKapoor, Hemangee Kalpesh
dc.publisher.placeGuwahati
dc.publisher.universityIndian Institute of Technology Guwahati
dc.publisher.institutionDepartment of Computer Science and Engineering
dc.date.registered2014
dc.date.completed2020
dc.date.awarded2020
dc.format.dimensionsNot Available
dc.format.accompanyingmaterialNone
dc.source.universityUniversity
dc.type.degreePh.D.
Appears in Departments:Department of Computer Science and Engineering

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